vivado の write_edif
たいしかことないLチカを edif 出力してみる。
(edif sw_led (edifversion 2 0 0) (edifLevel 0) (keywordmap (keywordlevel 0)) (status (written (timeStamp 2015 06 09 02 30 47) (program "Vivado" (version "2015.1")) (comment "Built on 'Mon Apr 27 19:22:08 MDT 2015'") (comment "Built by 'xbuild'") ) ) (Library hdi_primitives (edifLevel 0) (technology (numberDefinition )) (cell ODDR (celltype GENERIC) (view netlist (viewtype NETLIST) (interface (port Q (direction OUTPUT)) (port C (direction INPUT)) (port CE (direction INPUT)) (port D1 (direction INPUT)) (port D2 (direction INPUT)) (port R (direction INPUT)) ... 続く || S 式ですよ。当然 chicken で読めます。 >|scheme| (define sw-edif (call-with-input-file "sw_led.edif" (lambda (list-port) (read list-port)))) (print sw-edif)
キーワードだけ拾い出すと、hdi_primitives というライブラリ(Xilinx のデフォルトのライブラリ?)
(cell ODDR (celltype GENERIC) (cell GND (celltype GENERIC) (cell IBUF (celltype GENERIC) (cell VCC (celltype GENERIC) (cell INV (celltype GENERIC) (cell RTL_REG__BREG_5 (celltype GENERIC) (cell RTL_EQ0 (celltype GENERIC) (cell RTL_EQ1 (celltype GENERIC) (cell RTL_EQ2 (celltype GENERIC) (cell RTL_EQ (celltype GENERIC) (cell RTL_SUB0 (celltype GENERIC) (cell RTL_SUB (celltype GENERIC) (cell RTL_SUB2 (celltype GENERIC) (cell RTL_SUB1 (celltype GENERIC) (cell RTL_MUX3 (celltype GENERIC) (cell RTL_MUX5 (celltype GENERIC) (cell RTL_LATCH (celltype GENERIC) (cell RTL_REG_ASYNC__BREG_1 (celltype GENERIC) (cell RTL_REG_SYNC__BREG_2 (celltype GENERIC) (cell RTL_MUX1 (celltype GENERIC) (cell RTL_OR (celltype GENERIC) (cell RTL_INV (celltype GENERIC)
register とかは RTL_REG になるみたい。
RTL_REG は次のようになる。
(cell RTL_REG__BREG_5 (celltype GENERIC) (view rtl (viewtype NETLIST) (interface (port C (direction INPUT)) (port D (direction INPUT)) (port Q (direction OUTPUT)) ) (property XLNX_LINE_COL (integer 525568)) ) )
C, D, Q があるからつないでいけばよいという事ね。あとは RTL_SUB とかあるから、これつなげばいいのね。chicken scheme でなんとかできないか?ってのが今後の(どーでもいい)テーマ。